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דרושים Rfic Design Engineer ב-אפל ב-United States, Waltham
מצאו את ההתאמה המושלמת עבורכם עם אקספוינט! חפשו הזדמנויות עבודה בתור Rfic Design Engineer ב-United States, Waltham והצטרפו לרשת החברות המובילות בתעשיית ההייטק, כמו Apple. הירשמו עכשיו ומצאו את עבודת החלומות שלך עם אקספוינט!
חברה (1)
אופי המשרה
קטגוריות תפקיד
שם תפקיד (1)
United States
אזור
Waltham
נמצאו 84 משרות
26.08.2025
A
Apple Design Verification Engineer United States, Massachusetts, Waltham
תיאור:
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
- BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent
- Working knowledge of OOP, SystemVerilog and UVM
- Working knowledge in developing scalable and portable test-benches
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
- Experience with power-aware (UPF) or similar verification methodology
- Knowledge of one of the scripting languages such as Python, Perl, TCL
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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משרות נוספות שיכולות לעניין אותך
26.08.2025
A
Apple CPU Power Engineer United States, Massachusetts, Waltham
תיאור:
As a CPU Power Engineer, you will have the following responsibilities:• Analyze and estimate the power impact of implementing new micro-architectural features• Generate power rollups and projected estimates from initial to mature net lists through the lifecycle of a project• Analyze power contributions to generate opportunities for recovery in physical implementation as well as RTL• Create power projections factoring in expected cost of convergence and implementation and refine the process
- Minimum BS and 10+ years of relevant industry experience
- Perl/Python and TCL scripting experience from industry usage
- Experience with CPU architecture and implementation
- The ideal candidate should have broad knowledge related to micro-architecture, physical implementation, auto place and route tools, STA, spice, logic design, and device physics
- Knowledge of logic design principles along with timing and power implications for high performance and high frequency designs
- CMOS circuit design and analysis skills
- Experience with industry standard power analysis tools like PrimePower and PowerArtist
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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26.08.2025
A
Apple Design Verification Engineer United States, Massachusetts, Waltham
תיאור:
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all fields (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:- Neural Engine hardware- DRAM subsystem, memory controller logic- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1- Hardware security, including cryptographic algorithm implementations- High-Speed IO standards such as PCI Express, DisplayPort, MIPI- Power management and fabric infrastructure- Memory cache management- Display Subsystem for variety of panels and products
- Minimum of BS + 3 years relevant industry experience.
- Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
- Knowledge of SystemVerilog, digital simulation and debug
- Knowledge of computer architecture and digital design fundamentals
- Good SW programming skills with knowledge of data structures and algorithms
- Experience with Python, Perl, or similar scripting language
- Ability to work independently to deliver the project goals
- Knowledge of verification methodologies like UVM
- Experience with C/C++, assembly is a plus.
- Excellent interpersonal and communication skills and the dream to take on diverse challenges.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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26.08.2025
A
Apple RFIC Design Engineer United States, Massachusetts, Waltham
תיאור:
In this highly visibility role, and as part of our team, you will have responsibilities on researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Responsibilities include:• Design of analog and/or RFIC blocks.• Overseeing the layout and verifying the design to ensure a successful tape-out.• Overseeing the test and characterization of the design, and debugging issues that may arise from early development stages through productization.• Working with the system team to define the requirements for RF and baseband blocks based on the system requirements.• Working with the technology team to understand the capabilities and limits of the technology node to achieve the optimum performance.
- BS and 10+ years of relevant industry experience.
- RF/analog and mixed signal design experience in RF CMOS design.
- RFIC circuit design.
- Direct tape-out experience with one or more of the following blocks: RF front-end circuits, PA, LNA, mixer, oscillator, PLL, LO, VGA, filter, ADC/DAC, TIA or other baseband analog blocks in deep sub-micron CMOS technology.
- Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
- Deep understanding of CMOS device physics, RF device modeling, device noise parameters, inductor modeling, and circuit layout for optimum RF performance.
- Familiarity with various RF transceiver architectures and their trade-offs.
- Familiarity with Cadence Virtuoso, Spectre RF, EMX and similar tools.
- Experience in Si characterization and debug.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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25.08.2025
A
Apple Mixed Signal Circuit Design Engineer United States, Massachusetts, Waltham
תיאור:
As an Analog/Mixed-Signal Circuit Design Engineer, you will be involved with all phases of high-performance PHY designs from architectural concept to delivery of our final GDS.
- BS degree in technical discipline with minimum 10 years of relevant experience.
- Proven understanding of all aspects of Analog/Mixed Signal Circuit Design of PHYs. TX, RX, Delay Locked Loops, Phase Interpolators, Delay Lines, Duty Cycle Correctors, reference generators, etc.
- Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design team.
- Solid understanding of Circuit Verification tools (Simulators, Extraction, EMIR, Noise, SigEM, etc.).
- Generate block/chip level specifications.
- Perform block level verification to close the design by meeting performance, power and area specifications.
- Participate in establishing Design Methodologies to ensure correct, by construction designs.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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25.08.2025
A
Apple SerDes Circuit Design Engineer United States, Massachusetts, Waltham
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE with 10+ years of proven experience.
- The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
- Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Deep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
- Proven experience working on system and architecture teams to drive block-level and IP requirements
- Proven track record working with large teams and guiding junior engineers
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
- Experience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
- Experience with EQ adaptation methods and circuit interactions to improve PPA
- Solid understanding of CDR architectures and implementations
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
- Hands-on experience to drive lab testing, debug and data analysis
- Hands-on experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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25.08.2025
A
Apple CPU Cache Microarchitect/RTL Engineer United States, Massachusetts, Waltham
תיאור:
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification. • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals. • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for formal verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance. • Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power.
- Minimum BS and 10+ years of relevant industry experience
- Knowledge of microprocessor architecture
- Knowledge of Verilog and/or VHDL
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Expertise in one or more of the following areas:
- Coherence protocols and interconnects
- High performance (low latency, high bandwidth) design techniques
- Memory subsystem queuing, scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers, replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
- Experience using an interpretive language such as Perl or Python
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Expand
תיאור:
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
- BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent
- Working knowledge of OOP, SystemVerilog and UVM
- Working knowledge in developing scalable and portable test-benches
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
- Experience with power-aware (UPF) or similar verification methodology
- Knowledge of one of the scripting languages such as Python, Perl, TCL
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Expand
משרות נוספות שיכולות לעניין אותך
בואו למצוא את עבודת החלומות שלכם בהייטק עם אקספוינט. באמצעות הפלטפורמה שלנו תוכל לחפש בקלות הזדמנויות Rfic Design Engineer בחברת Apple ב-United States, Waltham. בין אם אתם מחפשים אתגר חדש ובין אם אתם רוצים לעבוד עם ארגון ספציפי בתפקיד מסוים, Expoint מקלה על מציאת התאמת העבודה המושלמת עבורכם. התחברו לחברות מובילות באזור שלכם עוד היום וקדמו את קריירת ההייטק שלכם! הירשמו היום ועשו את הצעד הבא במסע הקריירה שלכם בעזרת אקספוינט.