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Google SoC RTL Design Engineer India, Karnataka, Bengaluru 996181783
10.06.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in RTL coding using Verilog or Systemverilog language.
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Science, or a related field.
- Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
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