Qualcomm FY25 Intern - Low-Power AI Audio Sensors Subsystem 

Canada, Ontario, Markham 

991053451

Job Area:

Interns Group, Interns Group > Interim Engineering Intern - HW

As an ultra-low power subsystem, we innovate by enabling new functionality and use cases and optimizing for power with scalable performance for the Mobile, IOT, Wearables and AR/VR market.

Similarly, our High-Performance AI and Audio Subsystem ( HPASS) fuses the same compelling IPs into HW solutions designed for Autonomous Driving ( ADAS ), In-vehicle-infotainment and Telematics

Minimum Qualifications:

• In study towards a bachelors in one of the following: Electrical Engineering, Computer Engineering, Computer Science or related field . Must have a minimum of one semester of university remaining after the internship concludes. Cannot be graduating before internship begins.

• Knowledge of a programming language and scripting. Preferably some experience with lab equipment - scopes, etc. School projects with FPGAs a nice to have.

• Good communication skills, Teamwork and organizational skills

• Object Oriented Programming (OOP), C, C++, Digital Circuits

• Computer Hardware (Caches, Busses, Memories, Clocking)

Preferred Qualifications:

• UVM, SVTB, System Verilog

• I2S/PCM Protocols

• Mathematics for Machine Learning (Algebra and Geometry )

• Relevant courses in Digital Signal Processing, Digital Filters

• Familiar with Embedded systems and interconnects

• Familiar with perforce and other software development tools

• FPGA fundamentals

• Familiar with Python

For LPAI/HPASS ASIC Design and Implementation, Key Responsibilities/Exposures include:

• Contribute to RTL (Verilog) design for next generation Snapdragon Display Processors.

• Integration of external IP’s and design of interfacing logic into the Display Subsystem.

• Work with the latest sub-micron technology nodes.

• Use industry standard CAD tools for RTL Linting, power analysis, and CDC Analysis. Develop a strong foundation in good digital design practices.

• Participate in experiments to optimize the Display design across power, area, and performance targets.

• Using scripting languages (python) to enhance existing methodologies, automate manual processes, and devise new tools for design development.

For LPAI/HPASS ASIC Design Verification Intern, Key Responsibilities are/Exposures include:

• Own IP core level feature verification during the design and development phase of next generation ASICs through C/RTL and Gate Level simulations.

• Learn and get in-depth experiences with Display technologies and advance verification methodology and tools

• Participate in test plan development and execution and verification closure in conjunction with the ASIC teams.

• Contribute to creating/maintaining a test bench, assertions, and functional coverage models.

• Contribute to implementing flows to automate development processes.

• Participate in debug activities throughout the development cycle.

• Explore the capabilities of our simulation tools to help improve our DV workflow and simulation performance.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.