Intel SoC Director 

India, Karnataka, Bengaluru 

990689219

About the Role

We are seeking an exceptionally motivated and experienced Silicon Development Engineer to lead thearchitecture/micro-architecturedefinition and design of complex System-on-Chip (SoC) solutions. This role demands extensive understanding of SoC Architecture, Digital IP, and Network-on-Chip Interconnect design, coupled with significant pre/post-silicon debug expertise. The successful candidate will be instrumental in defining and implementing chassis architectures for advancedhigh-compute/performanceSoCs.

Key Responsibilities:

• Leadarchitecture/micro-architecturedefinition for advanced high performance SoCs, including chiplet-based designs supporting high throughput die to die coherency.
• Define and implement a scalable & high compute Chassis architecture for AI based consumer and server SoCs
• Drive micro-arch and design for high PPA solutions with optimised clock, reset, power for high compute SoC designs.
• Define end-to-end QoS solutions for multiple traffic class systems and implement low-latency, Head of Line blocking-free high throughput networks with complete freedom from interference
• Oversee SoC Chassis architecture, including Fabrics, SMMU & Access control
• Define Coresight compliant Debug and trace architecture for the chassis & SoC
• Work with design team to manage full-chip implementation of SoCs, encompassing Interconnect, SMMUs, Reset, Clocking, IO Mux, Debug-Trace, and High-Speed & Low speed IO Peripherals
• Work with Physical design teams to define the right SoC/Chassis partitioning, floor planning for a highly scalable SoC solution
• Drive project management, leading functional teams, and managing cross-functional multi-site projects.

Minimum Qualifications

BS in electrical engineer or computer science with 12+ years of experience

8+ Years of in silicon development engineering, with a strong focus on complex SoC Architecture.

5+ years of experience in experience in pre/post silicon debug.

5+ Years of experience with Memory & High-Speed interfacing

Deep understanding of Full chip System bus/fabric architecture (Coherent & Non-coherent).

Proven expertise in building SoCs with complex traffic class system with real time high throughput traffic management.

Strong background in Synthesis & Timing Analysis (Design Compiler/Primetime).

Experience with SOC Partitioning & Floor planning & strong awareness of technology nodes.

Preferred Qualifications

Strong understanding of latest DIE2DIE interfaces like UCIE & high-speed peripherals (PCIE) & Low speed peripherals (UART, SPI, CAN)

Solid knowledge of Multi-core infrastructure & IPC communication for efficient & performance SoC (looks good)

Proficiency with Simulation, Validation, and Signoff tools (IUS, Verdi, CDC, RDC, Lint).’’ (looks good)

Experience with 3nm chiplet-based SoC & chassis architecture.

Familiarity with UCIE based chiplet designs.

Hands-on experience with AMBA/CHI/UCIE/PCIE compliant High throughout interconnects.

Prior experience in leading microarchitecture and design forconsumer/wireless/automotive/ServerHPC SoCs.

Proven track record of defining and implementing low power, isolation & power management architectures.

Experience with third-party IP evaluation and liaison

Experienced HireShift 1 (India)India, BangaloreThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.