Work closely with wafer foundries and various functional groups such as Design, Advanced Technology Group and Operations to develop process reliability requirements for new technology nodes.
Drive foundries for NVIDIA’s test vehicle qualifications and process reliability improvement before taping out new products and support product bring-ups and quals.
Perform wearout reliability assessments and provide reliability guidance to design teams for Design for Reliability on the next generation products.
Provide reliability Vmax, aging guardband guidelines to product teams and develop reliability methodology to optimize product reliability performance.
Collaborate with foundries to plan and perform stress tests, and build reliability models for extrinsic failure mechanisms.
Interact with foundries for excursion materials and assess a reliability risk for disposition.
What we need to see:
Deep understanding of cutting-edge semiconductor process technologies, reliability physics, and acceleration models.
Familiar with wearout failure mechanisms (TDDB, BTI, HCI, EM, SM) and models, wafer level reliability tests, test structures, and industry standards (JEDEC, AEC).
Proficient in reliability statistics, and hands on experience in failure rate calculations for early life, useful life and wearout period of reliability life curve.
Good knowledge of semiconductor process defects/root causes, failure analysis and defect screening methodologies.
Solid understanding in circuit reliability and reliability degradation mechanisms.
Hands on skills in reliability data analysis, particularly using statistical tools such as JMP.
Capability of multi-tasking with priority.
Excellent written and verbal communication, and presentation skills.
Familiar with fab-less business model.
Participation in industry standard committees such as JEDEC, AEC and ESDA is a plus.
PhD or MS in Electrical Engineering, Physics, or a related major (or equivalent experience).
5+ years of overall experience in semiconductor reliability.