Intel Mask Design Engineer 

Taiwan, Taiwan Province, Hsinchu 

968678601

Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bit cells, SRAMs, Register Files).

Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.

Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), self-heat, ESD, and other reliability checks.

Uses custom auto routers and custom placers to efficiently construct layout.

Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.

Develops and drives new and innovative layout methods to improve productivity and quality.

Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

5+ years of experience with proven record of delivering high quality layout.

Expertise in Cadence Virtuoso EDA tools and familiarity with UNIX environment.

Collaboration and team lead skills.

Engineering problem solving and analytical skills.

3+ years of design experience in analog and standard cell layout design is a plus.

Experience with scripting languages like PERL, TCL, shell, SKILL, or Python is a plus.

Experienced in advanced node technology is required.