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Intel SOC Design Engineer Bolivia, Santa Cruz, San José de Chiquitos 966852252
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.
You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Bachelor's degree in electronic, Electrical, Mechatronic engineer, computer science, or related field of study with 2+ years of experience in:
Programming in Python or equivalent languages (packages, classes, methods and properties).
VLSI Logic design or verification - Major EDA tools (e.g., Synopsys VCS/Fusion Compiler/Spyglass, Cadence
Conformal/Xcelium, Siemens Mentor Graphics Tessent, etc.)- Unix/Linux and Windows operating systems
Intermediate English Level
Costa Rican unrestricted work permit.
Preferred Qualifications:
Knowledge in any of the next areas is a plus:
System Verilog / OOP, OVM/UVM.SOC-level design/integration and/or validation.
RTL quality checks.
Simulation-based debug (VCS, Verdi, DVE).
Computer (CPU) and/or System (Platform) Architecture.
Object Oriented programming.
Front-end Design TFMs (Tools, Flows, and Methodologies).
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