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Google ASIC RTL Design Manager Silicon India, Karnataka, Bengaluru 965009413
27.01.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
- 15 years of experience in ASIC RTL design.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience driving multi-generational roadmap for IP development.
- Experience leading interconnect IP design team for low power SoCs.
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