Conducting synthesis, physical design, and implementation activities for SoC design involving Arm CPU cores, system interconnect, and various Arm IP components.
Performing detailed analysis of design timing, area utilization, and power consumption to drive design improvements.
Develop new methodologies to improve implementation efficiency and results.
Collaborating closely with implementation teams, RTL design teams and physical IP teams to conduct comprehensive analysis and ensure the delivery of best-in-class design implementations.
Translating research and development concepts into practical implementation solutions.
Supporting and enabling partners to attain efficient quality outcomes.
Required Skills and Experience :
Bachelors/Masters with 3-8 years of minimum experience in Physical Design domain.
Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies.
Strong understanding in the RTL2GDSII flow for leading or mainstream process technologies.
Good understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure.
Expertise on optimizing for cost functions like performance, power and/or area is like gold dust.
Working experience with tools like DC/Genus, ICC2/Innovus, Primetime/Tempus and others relevant for physical implementation.
“Nice To Have” Skills and Experience :
Any implementation experience on Arm CPU and GPU IP designs would be excellent.
High-level know-how related to foundation IPs like standard cells and memories fits well with our work.
Good automation skills in PERL, TCL and EDA tool specific scripting can be impactful.