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Intel Lead Graphics Post Silicon Low Power Validation Engineer India, Karnataka, Bengaluru 957308184
11.03.2025
Job Description
- Lead low power validation strategy and drive validation roadmap across multiple projects
- Lead a very high performing team of talented engineers working on GPU IP post-Si low power validation
- Excellent understanding latest GPU architecture/micro-architecture low power features, design changes and develop Post-Si Low Power validation test plan for 3D/Compute pipeline
- Very good understanding of low power concepts and flows (dynamic, leakage power, clock gating, power gating, Resets, stand-by entry/exit flow, DVFS, clock squashing, TDP, PM flexing)
- Good understanding of power switching, isolation, level shifter, clock domain crossing, PLL, power delivery logic
- Understanding of low power FSM blocks, states and interfaces with microcontrollers, SW Driver, FW, SoC and platform
- Define low power validation scenarios and implement basic/stress/concurrency/cross-feature/PM cycling/random test cases
- Work closely with pre-Si architect/design/verification and SW/FW teams to review test plans and scenarios and finalise synthetic/BareMetal/driver/real use cases to validate on simulation/emulation to sanitize tests before Si arrival
- Analyse feature coverage gaps and enhance test plans
- Define power-on bring up and volume validation regression plan to enable PRQ.
- Come up with receivables/dependencies, Risks/mitigation and follow-up closely with relevant stakeholders for closure
- Debug: Understand Si failure signatures in-depth, work closely with design and architecture, SW/FW teams to root cause issues. Guide juniors on debug
- Tools : Advance usage of Si debug tools.Work with tool development teams to Develop tools/scripts. Effective reproduction of issue on Emulation/simulation to decrease debug TAT
- Innovation – Drive development of new low power validation methodologies, shift-left validation, PM test framework, automation tools (test content generation, debug, feature coverage) and adoption of AI/ML methods to improve efficiency
- Regular Rolling up of the Post Si low power validation status to the upper management for decisions at various product cycle milestones
- Master of Engineering degree in Computer or Electronics or Embedded Systems Engineering with 7+ years' experience in graphics post silicon power management
- PhD degree in Computer or Electronics or Embedded Systems Engineering with 5+ years' experience in graphics post silicon power management
- Should have good understanding of Computer architecture, Graphics architecture/design, low power Validation and Si Debug Flow
- Hands-on experience in C/ C++, and Perl/Python, Linux Shell Scripting
- Familiarity with Verilog/System Verilog/VHDL
- Familiarity with Windows, Linux OS, commands and environment
- Familiarity with OpenCL, OpenGL, Vulkan and DirectX API programming is desirable.
- Good analytical ability, problem solving, and written and verbal communication skills
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