Bachelor's degree in Electrical Engineering or equivalent practical experience.
10 years of experience in micro-architecture and design of graphics or Machine Learning (ML) Internet Protocols (IP), handling Low Precision/Mixed Precision Numerics.
5 years of experience architecting networking Application-Specific Integrated Circuits (ASIC) from specification to production.
Experience developing Register-Transfer Level (RTL) for ASIC subsystems using SystemVerilog.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience in System on a Chip (SoC) designs and integration flows.
Experience working with software teams optimizing the hardware/software interface.
Experience estimating performance by analysis and modeling, and defining and driving performance test plans.
Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Proficiency in a procedural programming language (e.g., C++, Python, Go).