Required/Minimum Qualifications
- 9+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
- 4+ years of industry experience in design verification involving Ethernet protocol with a proven track record of delivering complex IPs toApplication-Specific Integrated Circuitor System on Chips.
Other Qualifications:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Additional or Preferred Qualifications
- 15+ years of industry experience in design verification with a proven track record of delivering complex SoC IPs.
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
- DV and optional design Experience with integration of Ethernet IPs into SoCs. Experience working with 3rdparty IP vendors.
- Experience with IP/SOC verification for a full product cycle from definition to silicon, including writing IP/block or subsystem level architecting DV environment, estimating efforts, test plans, developing tests, debugging failures and coverage signoff.
- Experience of working on AI/Machine Learning (ML)SoCs.
- Experience in post-silicon bring-up of complex SoCs involving Ethernet interface.
- In depth knowledge of verification and debug principles, test benches, System Verilog, Universal Verification Methodology (UVM) and C based test environments.
- Experience in IP level, subsystem level and SoC level verification environments; and verification IP vertical reuse across multiple levels.
- Working knowledge of writing assertions, coverage and / or formal verification.
- Knowledge of industry standard bus interfaces such as Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) and Ethernet protocols.
- Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
- Scripting languages such as Zsh, Bash, Python or Perl.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until June 14 , 2024.