- As a member of our Physical Design team in this highly transparent role, you will directly own implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC using brand-new process technology- You are going to own block level PnR, floor-planning, clock and power distribution- You will get involved with static timing closure with commercial tools- You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS)- You will be developing and validating dedication low power clock network guidelines- With phenomenal focus you will resolve design and flow issues related to physical design, and identify potential solutions whilst driving execution- You know what documentation should look like, and will help with guidelines and specs