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Mobileye VLSI Fronted Backend Engineer Israel, Haifa District, Haifa 932425406
04.03.2025
What will your job look like:
- You will be responsible for the Synthesis output quality we deliver to the backend team for implementation
- Develop and maintain the timing constraints and physical constraints
- Debug failures and provide feedback to both RTL and BackEnd teams to rich convergence with high confidence at early stages
- Define, run and debug CDC analysis
- Be involved in back-annotated timing Gate-Level simulations.
All You need is:
- BSc or MSc degree in Computer Engineering or Electrical Engineering.
- Hands-on experience of 3 years or more in logic synthesis, Design-Compiler or Fusion-Compiler are preferable
- Proven experience in defining timing constraints.
- Understanding of BackEnd implementation process
- Basic experience with Verilog HDL
- Wide knowledge of DFT concepts.
- Practical experience in Tcl scripting language
- Experience with Python and/or Perl scripting languages - Advantage
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