Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience with different verification techniques and methodologies including formal, GLS, UPF based Power simulations, UVM and C based testing to achieve bug-free Silicon in SoCs.
Experience in ARM and RISC-V processor based DV including tool chains and C based testing.