Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Participates in the definition of architecture and microarchitecture features of the block being designed
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features
Supports SoC customers to ensure high quality integration and verification of the IP block
Drives quality assurance compliance for smooth IP SoC handoff
Qualifications
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience
Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components
Knowledge of Power management is preferred. Experience with formal apps would be good. Expertise in Verilog and System Verilog-based logic design. Expertise in Verilog and System Verilog-based logic design
Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must
Knowledge of considerations for performance, power, and cost optimization is desirable. Knowledge of formal property verification using Jasper is preferred
Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills
Set aggressive goals and meet/beat the commitments
Flexible enough to work in a dynamic environment and multitask seamlessly. Ability to work independently and in a team
Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage