Microsoft Sr Silicon Engineer -Logic 

India, Karnataka, Bengaluru 

918912701

engineers to help achieve that mission.

Cloud Compute Development Organizationis instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

SOCRTL to

• MS with 2+ years of experience or BS with 4+ years of experience.
• Atleast 2+ years of experience applying digital design principles in SOC and/or IP development.
• Strong Static Timing Analysis background; understanding timing signoff fundamentals.
• Experience in EDA tools such as Primetime,StarRC, Design Compiler, ICC, and Innovus.
• Experience with timing constraints management anddebugtools supporting constraints quality checks, constraints verification, constraints promotion & demotion.
• Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints.
• Understanding in design closure challenges in power and clock domain crossings.
• Understandingreset and FIFO related design requirements.

Preferred Qualifications

• Experience withFEV and industry standard tools such as Formality and/or Conformal
• Applied understanding of low power design principles.
• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Strong understanding in clock crossing techniques
• Strong understanding in IJPF (Low power intent).
• Ability to write scripts using Perl, TCI, Python etc.
• Familiarity with Industry standard interface protocols is a plus.
• Good verbal and written communication skills.

• high quality deliverables from RTL toPhysical Design
• Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results
• Create,analyze, andmaintaintiming constraints/SDCs
• Analyzeand drive UPF solutions forlow power checks
• Drive RTL to SynthesisFEVclean
• Collaborate withRTL and Physical Design teamto address design feedback and drive quality