What you’ll be doing:
Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industry's leading GPUs
Design and implement RTL features (microarchitecture and RTL)
Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP
Co-work with verification engineers to sign off the design
Work with architects, designers, and SW engineers to accomplish your tasks
What we need to see:
MS in Electrical or Computer Engineering with 3 years of relevant industry experience
Have super scale project design experience.Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation
Good understanding of SOC architecture (e.g., CDC, multiple-power domains, performance analysis, latency, and data flow)
Have goodunderstanding/managementon task dependency and experienced in working at complex tree.
Strong coding skills in Perl or other industry-standard scripting languages
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Verdi, GDB)
Great communication and collaboration skills to interact within the team and with cross functional teams
Ways to stand out from the crowd:
Performance Monitor background
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