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Cisco Hardware Engineer Student Israel, Haifa District, Hof HaCarmel Regional Council 902941336
Yesterday
What You'll Do
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
We are constantly offering several positions in the ASIC development field:
- Design and verification under the front-end design team
- Physical Design implementation team
- Signal integrity (SI), Power integrity (PI) and Lab post silicon electrical characterization
- Analog/Mixed Signal Design team
- DFT (Design for testing) design team
Minimum Requirements:
- B.Sc or M.Sc Electrical Engineering or Computer Engineering Student from leading Israeli Universities.
- Graduate in 2025-2026.
- GPA above 85. (Please attach your grade sheet when applying to expedite the recruitment process).
More information about each option:
- -Front- End Design team at Cisco Silicon One team. The team is leading the silicon development in Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro architecture, design, verification, sign-off and validation. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
- Physical Design Implementation Team-Physical Design team at Cisco Silicon One team. The team is leading the silicon physical implementation in Cisco. Our team deals with all physical design aspects from RTL to GDS: Synthesis, Place & Route, sign-off and physical verification. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
- Signal integrity (SI), Power integrity (PI) and Lab post silicon electrical characterization-Lab post silicon electrical characterization– very high-speed interfaces characterization and compliance to spec; silicon electrical validation including power, speed, process, and packaging thermal; high usage with lab high speed / RF equipment and automation.Signal integrity (SI) and Power integrity (PI)-SI of very high-speed interfaces. Layout escape and routes geometries extractions, optimization and sign-off to the spec. Frequency and time domain analysis. PI of very power hungry and analog sensitive supplies, impedance profile extraction, time domain analysis of latest SI/PI tools and flows. Close relations with the IP/Packaging/PCB teams for max optimizations and tradeoffs.Package designfrom bump map and spec to full netlist and layout implementation. Large scale, multi die complex structures. Design signoff including high speed routes, LVS, LVL, IR drop etc’. Close relations with the IP/PD/PCB teams for max optimizations of the package design.
- Analog/Mixed Signal Design Team-You will architect and design analog/mixed-signal circuits for a highly advanced high-speed IP on industry leading CMOS process nodes. The work content encompasses all design stages, from definition to final layout sign-off. You will join a small team of top industry analog and system professionals
- DFT Engineer- As DFT engineer you will be involved in the chip entire life cycle: both pre silicon and post silicon, taking part in bringing our product with high quality to our customers. It will be a big plus if you have experience in working on the DFT area from the definition via the design and up to full production.
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
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