Nvidia Chip Power Optimization Engineer 

India, Karnataka, Bengaluru 

901500957

What you’ll be doing:

• Architecture, development and correlation of power estimation models/tools for NVIDIA's chips

• Help architect and develop power models for use-cases, Idle power and IO power.

• Chip in to design the tools based on these models and their testingmethodology/infrastructures

• Correlate and Calibrate the power models using measured silicon data

• Analyze and help decide the chip configuration and process technology options to optimize power/performance for Nvidia's upcoming chips

• Help study and contribute to Performance/Watt improvement ideas for Nvidia's GPUs and SOCs

What we need to see:

• B.Tech./M.Tech and 2+ years of experience related to Power / Performance estimation and optimization techniques

• Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits

• Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)

• Strong background in power estimation techniques, flows and algorithms

• Good programming skills - Python preferred. Good skills with object-oriented programming and design.

Ways to stand out from the crowd:

• Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus

• Exposure to power analysis EDA tools such as PTPX/EPS

• Good communication skills & desire to work as a great teammate