Designs complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.Minimum Qualifications Currently a Masters (MTech/MS) student in VLSI, Electronics, Electrical Engineering or related discipline.Familiarity in scripting languages such as TCL, Python, and Perl.Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plusSelf-Motivated with good communication skills and strong problem-solving skills.Preferred QualificationsKnowledge in circuit design, layout, circuit reliability tools/methodologiesCoursework or Experience in semiconductor process flow, device layout and simple circuit operationDegree: MTech/MSSchools:Sl. No College Name1 IISc, Bengaluru2 IIT Madras3 IIT Bombay4 IIT Kanpur5 IIT Kharagpur6 IIT Delhi7 NIT Surathkal (NITK)8 NIT Calicut9 NIT Warangal10 NIT Trichy11 BITS, Pilani