Develops pre Silicon functional validation tests to verify system will meet design requirements.
Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.
In this highly visible and interactive role your primary responsibilities will include: Understanding given Graphics(Media, Display, Image Processing Unit), AI (Neural Processing Unit), DFD (design for debug), D2D/Ucie cross-die interface and SoC Power Management clusters u-architecture understanding, SoC/SS Integration or IP test plan development, SOC/Subsystem/IPs Test-Bench infra.
Definition/development, Val content (test/sequence/cov/assertions) development and signing off all define Verification milestones for Regression/coverage side.
Qualifications
BE or B Tech or M Tech ECE or Computer Science with 5-10 years SoC ,Subsystem ,IP verification experience.
Minimum 5 to 10 year of relevant experience in SoC/Sub-system/IP integration and verification ie developing IP verification components, integrating IP verification content to SOC/SS preparing and executing test plan for complex clusters, subsystems.
Good understanding and working experience in System Verilog/UVM, Verilog and scripts perl shell Knowledge and hands on experience in Industry Standard Verification Methodologies eg UVM.
Hands on experience in Industry standard simulation and debugging tools ie VCS and Verdi etc.
Working experience and good understanding of state of art verification technologies i.e .coverage and assertion based formal verification and HW assisted verification.
Good understanding of Graphics(Media,Display,IPU), AI [NPU], DFD (design for debug), D2D/Ucie and Power Management clusters.