Intel SoC Design Debug DFD Intern 

India, Karnataka, Bengaluru 

887443832

In this role the student/intern would be working as part of a design for debug team for future Intel SoCs and IPs. Responsibilities include but not limited to validation of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA, creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide, learning the Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause, developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design, participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models, and developing debugging tools and software.Minimum Qualifications Currently a Masters (MTech/MS) student in VLSI, Electronics, Electrical Engineering or related discipline.Familiarity in scripting languages such as TCL, Python, and Perl.Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plusSelf-Motivated with good communication skills and strong problem-solving skills.Preferred QualificationsKnowledge in System Verilog, IP-level design/verification is a plus.Simulation-based debug (VCS, Verdi, DVE).Computer (CPU) and/or System (Platform) Architecture.Emulation at SoC and/or Platform level.Firmware and/or boot development/debug.Front-end Design TFMs (Tools, Flows, and Methodologies)Degree: MTech/MSSchools:Sl. No College Name1 IISc, Bengaluru2 IIT Madras3 IIT Bombay4 IIT Kanpur5 IIT Kharagpur6 IIT Delhi7 NIT Surathkal (NITK)8 NIT Calicut9 NIT Warangal10 NIT Trichy11 BITS, Pilani