As an SoC Performance Engineer you will be working on the boundary of pre-silicon performance modeling and post-silicon power and performance tuning and debugging. You will be responsible for tuning and architecting enhancements to HW+SW power/performance control systems and policies in new products. You will build novel HW+SW data capture and analysis tools for yourself and others to gain insight into how our chips are used under iOS, macOS, and more. You will build meaningful new capabilities into our C++ SoC performance models in the areas of use case capture (on silicon) and playback (in the model), and modeling of power-relevant hardware and software features like DVFS and clock/power gating. You will work closely with IP and chip architects on high-impact studies to define future SoC features in the areas of on-chip interconnect fabrics, shared caches, DRAM controllers, and more.