Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level, cluster level, and full chip level
Collaborate with CAD team to optimize & smooth our simulation flow
Generating test patterns and perform chip bringup
What we need to see:
Master degree of Electrical Engineering/Computer Engineering/Computer Science
2+ years of DFT or design experiences
Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS).
Familiarity with SOC basicarchitecture(clock,reset,powerrail,IO pad,package)
Understanding of Design for Testing including Scan/ATPG/BIST/JTAG is a plus