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Google ASIC RTL Design Engineer Silicon India, Karnataka, Bengaluru 882789228
25.03.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience in ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical/Computer Engineering.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
- Experience with methodologies for low power estimation, timing closure, synthesis.
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