Job Description:- You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
 - In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks.
 - Your responsibilities will include but not limited to and nbsp
 - Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
 - In depth understanding of different memory design concepts ((SRAM/RF/ROM).
 - Expertise in Static timing analysis concepts.
 - Close work with Layout and Floor planning teams.
 - Back end design implementation of new features and nbsp.
 - Expertise in Memory post silicon analysis.
 - Good understanding of statistical variation.
 - Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores.
 
Qualifications:- You must possess a master's degree in electrical or computer engineering with atleast 8 or more years of experience in related field or a bachelor's degree with atleast 10 years of experience.
 - Technical Expertise in synthesis, P and R tools preferred.
 
Preferred Qualifications:
- Digital Design Experience, with High Speed, Low Power.
 - Familiarity with Verilog/VHDL.
 - Tcl, Perl, Python scripting.
 - Good understanding of spice simulations and analysis
 - Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills.
 - Experience in design & verification of high-speed clocks.
 - This role requires hands-on knowledge with hierarchical designs, budgeting of latencies and skews.
 
Experienced HireShift 1 (India)India, Bangalore