What you’ll be doing:
Develop strategies and infrastructure for next generation HSIO bring up, validation and product integration with a deep understanding of IO design, specs, use case and topologies.
Ensure interoperability with connected devices and system components in complex interconnect topologies
Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
Work on system level power strategies to continue pushing performance in power constrained systems
Work closely and proactively with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations and AE teams to drive design, development, debug and release of next generations products.
What we need to see:
BS or MS degree in EE/CE or equivalent experience
Minimum 2 years working in post-silicon bringup, HSIO Functional validation, and/or power optimisations.
Experience with HSIOs like PCIE or USB including understanding of process/temp/voltage sensitivity on BER
Experience with system level and interconnect power management optimisations.
Understanding of electricaltuning/performance/challengesof HSIO
Understanding of firmware/driver structures and their interaction with HW
Hands-on validation lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analysers)
Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis.
Excellent problem solving, teamwork, and interpersonal skills.
Background with automation scripting in languages such as Perl, Python, tcl,Experience with Linux
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