Microsoft Principal IP/SOC Design Engineer 

India, Karnataka, Bengaluru 

867151076

• 15+ years of related technical engineering experience

OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 15+ years technical engineering experience or internship experience

OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience or internship experience

OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience or internship experience.

• 10+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs.
• 10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
• 5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs

• 3+ years of experience with post-silicon debug
• 1+ years of experience with UPF

• 15+ years technical engineering experience

OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 15+ years technical engineering experience

OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience

OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience.

• 10+ years of experience working on IP design including architecture, microarchitecture, RTL coding, synthesis, verification, post silicon debug, interaction with DFT and PD team.
• 10+ years of experience in designing arbiters, switches in networking ASICs is a plus.
• 10+ years of experience in fabric design, complex arbiter designs, large width data bus designs
• 5+ years of familiarity with SOC/SS/top level integration and issues related to that.
• 10+ years of experience with LINT/Clock Domain Crossing (CDC)/Reset Domain Crossing (RDC) closure
• 5+ years of experience with Synthesis, Timing constraints and UPF
• 5+ years of experience in leading and managing a team of designers is a plus.
• Experience with industry standard interfaces such as AXI, APB, JTAG
• Experience with writing System Verilog assertions
• Experience with scripting languages such as Perl or Python
• Track record of successful tapeouts in deep sub-micron technologies
• Experience with multiple post silicon bringup and validation cycles

• Excellent communication skills and the ability to facilitate collaboration across Microsoft internal groups and external vendors

• Ability and willingness to adapt and work on variety of designs

You will be part of the IP/SOC design team driving many facets of high performance, high bandwidth designs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, System on Chip (SOC) integration including clocking and resets, Synthesis and static checks such as Lint and Clock/Reset domain crossings. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec.