Bachelor's degree in Electrical Engineering or equivalent practical experience.
2 years of experience in SOC/IP DV.
Experience with verification methodology such as SV and UVM.
Experience in ARM security architecture.
Preferred qualifications:
Familiarity with SoC level DV/UVM environment.
Knowledge of JTAG/APB/AHB/AXI based protocols.
HDL (Verilog/VHDL), HVL (System Verilog, OVM, ARM-C), and SVA (System Verilog Assertions) and experience with simulators and debug tools (VCS, NCVerilog, Novas)
Knowledge of ATE pattern generation/conversion, Virtual Tester simulation, and Bench CSV generation.