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Job Overview:
You know us. With 125 Arm-powered products shipped every second, we'll be in over a trillion smart devices by 2035.
Responsibilities:
As Staff Design Engineer, you will work on architecting and developing memory Fast Cache instances for our next generation Arm Cores achieving outstanding PPA.
Required Skills and Experience:
We Prefer graduate or postgraduate from a university or Engineering School, in Electronic Engineering Degree.
· You must have 8+ years of proven experience and track record in SRAM/memory designs, margin analysis, characterization and verification
· Expected to understand computer architecture concepts, FE models and Verilog
· Expected to understand high speed/low power CMOS circuit design, clocking schemes, Static, dynamic and complex logic circuits.
· Silicon validation experience with proven track record of debug
· Expected to have good leadership skills.
“Nice To Have” Skills and Experience:
Experience of working on Cadence or Synopsys flows and suggested enhancements
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