Intel SOC Floorplanning Lead 

India, Karnataka, Bengaluru 

818737971

Job Description:

We are looking experienced Floorplan Engineer to work on Foor plan, die estimation, Power planning of high performance designs . Responsibilities include

• Establishes the integration plans for die with optimization for package and board constraints.
• Bump planning, Die file generation , closing loop with package team on signal and power bump placement restrictions
• Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio.
• Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR.
• Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.
• Coordinate with power delivery team on trade-offs for metal allocation for signal and power.
• Have excellent understanding on,die-per-reticle/good-die-per-wafermaximization, and right technology selection on metal layers usage maximization
• Good knowledge on RDL routing and efficient usage higher metal layers
• Performs integration of all dies in a package and completes the relevant checks before tape-out.

Qualifications:

Qualification :

• 12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
• Must have led multiple SOCs in capacity of SOC Floorplan lead. Strong Expertise in Design planning, die estimation, Good understanding on package and board level requirement .
• Must have knowledge on clocking , high speed design signal routing, industry standard protocols and IP architecture;
• Good understanding on relevant areas of Library / Memory / technology/submicron issues .
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important

Experienced HireShift 1 (India)India, Bangalore