Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth and platform development kit (PDK) changes.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience with a scripting language like Perl or Python.
Experience in developing constraints and validating using Timing Constraints Manager (e.g., Synopsys) or TimeVision (e.g., Ausdia).