Intel SoC Design Verification Engineer 

India, Karnataka, Bengaluru 

799304192

Job Description:

Come join Intel's Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.Your responsibilities will include but not be limited to:

• Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA.
• Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
• Developing debugging tools and software.

Minimum Qualifications:

• Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience.
• Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others.
• Proven record of working across verification teams to solve problems.
• Expert of HW and SW Interaction and debug to root cause.
• Experience working across verification, architecture, SW, and design teams to resolve debug issues.
  Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans.
• Minimum 4years of SOC Verification or Functional verification.
• Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux.
• Minimum 2yrs experience with SOC Architecture.
• Must have 4yrs+ experience with SOC Verification or Functional Verification.
• Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team.

Preferred Qualifications

• Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture.
• Good to have working experience on assertions, coverage and Formal verification

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.