Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the logic/RTL design of IPs, SoCs, and thebetween IPs and SoCs. Defines methodologies that produce enhancements in power, performance, and area for designs on the new architectures and process technology nodes. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing logic/RTL related TFM. Works closely with the logic designer to create and enhance logic design methodologies that enable fast design convergence and facilitate seamless integration.Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.Basic knowledge of hardware description languages (HDLs) such as VHDL or Verilog.Understanding of digital design principles and methodologies.Prior internship or project experience in IP development or related areas is a plus.Experience with simulation and verification tools (e.g., ModelSim, Synopsys VCS) is a plus.Good analyzing and debug skills, and creative in problem-solving.Positive energy and highly motivated to learn and adapt to fast-evolving IP technologies and environments.College GradShift 1 (Malaysia)Malaysia, PenangMalaysia, Kulim