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Intel Senior CPU Design Verification Engineer Israel, Haifa District, Haifa 780268124
As a Senior ASIC Design Verification Engineer, you will work as part of a Development team on cutting edge design components that will require deep understanding of a highly complex design architecture.
You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verificationwhich includesdeveloping verification planning, test execution, through collecting and closing coverage.
Plan the verification of new design features by fully understanding the design specification and interacting with design engineers and architects to identify important verification scenarios.
Create and enhance constrained-random verification environments using UVM methodology. Be a part of design feature development cycle from planning to implementation and closure. Write or enhance verification components aimed for stimulus and checking of the design block. Debug tests with design engineers to deliver functionally correct design blocks. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage measures to identify verification holes and to show progress towards tape-out.
Qualifications
- BSc in Electrical or Computer Engineering from a leading University.
- 5 years or more of experience in Pre-Silicon Verification using UVM methodology.
- Knowledge in Very Large-Scale Integration (VLSI) design verification.
- Experience in Specman/SV (big advantage).
- Super strong RTL debugging skills.
- Skilled in functional coverage-driven verification.
- Experience in Perl/Python scripting (advantage)
- Great communication skills
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