Texas Instruments AMS Verification Lead Engineer 

India, Karnataka, Bengaluru 

77510951

What will you be doing in this role? (Responsibilities)

• Verification of complex analog designs/systems, support validation of the design on silicon.
• High quality, timely release of meticulously analyzed and simulated IC designs. These designs should lead to best performance, cost ­effective, high quality, bug­ free products that fully meet our customer’s end­ system requirements
• Definition, specification, modeling, planning and implementation of AMS verification strategy for mixed ­signal ICs (70+% Analog). ­ Implementation and debug of AMS verification environments, regression testing, reporting of results and coverage analysis.
• Write detailed verification plans to cover project requirements for top-level AMS functionality, and construct test cases exercising the plan.
• Evaluate system-level use-cases and re-create these in simulation.
• Enable high quality verification through efficient use of bug tracking tools and methods, including back-annotation of DV implementation into verification plan to show closure of functional requirements.
• Planning, leading and tracking of design & verification projects in a global organization
• ­Post layout parasitic extraction and simulation, verification of all IC level performance metrics­
• Contribute to continuous improvements for quality and efficiency on design verification strategy, tools, methods and flows.

Knowledge and Skills

• Strong background in defining and developing verification Infrastructure for Mixed Signal semiconductor products
• Good understanding of analog circuits, ability to come up with Analog Models required
• Expertise in Cadence Virtuoso, Cadence Spectre/ TISpice, Verilog- AMS/ System Verilog
• Thorough understanding of AMS simulations, digital RTL, analog schematics
• Exposure to supporting post silicon investigations to ensure silicon measurements match pre-silicon verification results
• Proficiency in Scripting languages and utilities including Python, Perl, etc.

Other

• Ability to work well with internal cross functional teams (systems, test, design, validation, applications, marketing, etc.) to resolve issues and generate business success.
• Problem solving and communication are important skills in this role.
• Ability to manage assigned tasks with minimal supervision and mentor early career engineers towards becoming successful verification designers.

Preferred Skills/ Experience

7+ Years’ experience in Mixed Signal verification

Skills: Virtuoso, Verilog, Verilog AMS, Cadence tools like xrun/ncsim/Vmanager

Minimum requirements

7+ Years’ experience in Mixed Signal verification

Skills: Virtuoso, Verilog, Verilog AMS, Cadence tools like xrun/ncsim/Vmanager