Nvidia Mask Layout Design Engineer - New College Graduate 

China, Shanghai 

752738397

What You'll Be Doing:

• Physical layout of STD cells, ROMs, and compiled RAMs on each most advanced foundry processes with earlier and unstable design environments.

• Work closely with NVIDIA talents to speed up layout production including customized DRC/LVS, and plenty of specific verification development, testing, and debug.

What We Need To See:

• Pursuing MS or PH.D. in MS Microelectronics, Semiconductor Physics or related field.

• You are familiar with Cadence Virtuoso, you're familiar with Siemens Calibre or Synopsis ICV, or similar design and verification tools.

• Experience working across teams and dealing the tasks in parallel.

• Excellent communication, problem-solving, and analytical skills to decompose complex issues and present them clearly and simply.

Ways To Stand Out From The Crowd:

• Knowledge of and experience with advanced FinFET/GAA processes

• Prior design experience involving Standard Cells and/or Memory structures

• Good English written, verbal, and presentation skills

• Scripting ability in SKILL and/or Perl