Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
Experience with a scripting language such as Perl or Python.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Domain knowledge in one or more of the following: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, or PinMux.
Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
Proficiency with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).