Work closely with the design team from early stages of the design process to review and define DFX architecture.
Define test methodologies for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Work with Test Engineers to define detailed requirements and test specifications to cover all SoC testability aspects.
Characterize test program across process/voltage/temperature (PVT) to define guard-bands to enhance test program stability to meet automotive quality requirements.
Lead debug and development activities with tier-1 Foundry and OSAT vendors to address all NPI and production issues. Drive remote debug activities, yield enhancement efforts, and test time/cost reduction initiatives.
Define requirements and deployment strategy for a comprehensive Yield Management System (YMS), to enable end-to-end. production traceability and effective yield monitoring across all stages of production stages. Provide periodic Yield status reports to senior management.
Define and review SBL (Statistical Bin Limits) and manage production test excursions in a timely manner.
Establish production test release procedure, own and manage OSAT release process.
Work closely with the Quality & Reliability to execute Silicon and Package qual activities.
All you need is:
BSc or MSc degree in Electrical Engineering.
7+ years of experience as IC Product/Test engineer.
Hands on experience in bring-up & productization of complex IC products.
Deep understanding of structural DFT methods (scan, mbist, jtag, …)
Experience with data and yield analysis using known statistical methods and tools (e.g. JMP).
Proficiency in C/C++ and scripting language (Perl, Python, …) in Unix environment.
Prior experience with advance Teradyne and/or Advantest ATE platforms – an advantage.
Familiarity with Verilog and RTL behavioral simulations – an advantage.
Team player, with the ability to work in a rapidly evolving environment.
Strong sense of ownership, commitment, and responsibility.