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Intel Global Yield FEOL Front-End-Of-Line Process Ireland 732653634
FEOL (Front-End-Of-Line) Integration Development engineers'responsibilitiesinclude (but not limited to):
Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.
Collaborate with Technology Development and Local Yield teams to import new technology to production fabs.
Work with FEOL/BEOL Integration, Device, Defect Reduction and Yield Analysis team members to identify root cause of yield/performance issues and implement mitigation plan in defined timeline to meet committed production yield/performance targets and to support fast paced yield ramp-up in high-volume manufacturing phases.
Perform feasibility studies, plan and conduct experiments to fully characterize the process throughout the development cycle and to improve performance for each specific product.
Own NPI (New Product Introduction) in production fabs and perform product-specific process optimizations to meet foundry customers specifications and requirements.
Own engineering projects in partnership with Local Yield teams to improve product yield, quality, device performance and to reduce wafer cost.
Engineering support for technical interactions with internal and external customers.
Candidate should possess the followingbehavioralskills:
Must demonstrate solid communication skills.
Ability to work with multi-functional, multi-cultural teams.
Demonstrated interpersonal skills including influencing, engaging, and motivating.
Problem-solving technique with strong self-initiative and self-learning capabilities.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
MinimumQualifications:
Bachelor's degree in science and engineering major, with at least 12 years of experience in advanced node semiconductor industry in FEOL Process Integration (preferably in one (or more) of the following segments: Fin, Gate or PC, Spacer/Source-Drain or Junctions, RMG (Replacement Metal Gate), Contact / MOL (Middle of the Line)). Level of experience will be considered in determining applicants job grade.
Working level understanding on Device Physics and experience in advanced nodes (FinFET technology, GAA (Gate-All-Around)) in development or high-volume manufacturing.
Basic understanding and collaboration experience with processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.
PreferredQualifications:
Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, Chemistry or Materials Science major is preferred, with at least 8 years of experience.
Experience in project/program management and/or Task Force Team lead.
Ability to leverage big data analysis to identify process design weaknesses and/or manufacturing weaknesses in order to propose corrective, data-based solutions.
Ability to extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics and machine learning.
Experience in new semiconductor technology development.
Experience in serving external Foundry customers through technical interactions.
Experience in GAA (Gate-All-Around) technology architecture.
Experience in Statistics and Machine Learning.
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