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Apple Early Career - Front-End Implementation Engineer 
United Kingdom, England, London 
72782882

06.07.2024
Minimum Qualifications
  • Minimum of BSc in EE.
  • Experience with physical synthesis, including logic and PPA optimisation techniques.
  • Understanding and application of physical design and static timing analysis principles.
  • Proficient in Verilog and/or System Verilog and scripting languages.
Preferred Qualifications
  • Familiarity with DFT insertion;
  • Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level;
  • Experience implementing ECOs for functionality and timing.