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Google Lead CPU RTL Design Engineer Silicon 
Taiwan, New Taipei 
707257068

24.06.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
  • Experience with CPU or AI accelerator integration with SoC.

Preferred qualifications:
  • PhD in Electrical Engineering or Computer Science, or a related field.
  • Experience leading front-end design for modern processor components or AI accelerator.
  • Experience with ARM Instruction Set Architecture.
  • Experience with SoC design, architect and integration.