Nvidia ASIC Top Floorplan Design Engineer 

China, Shanghai 

692140588

What you will be doing:

• Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development.

• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.

• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

• Build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

What we need to see:

• Master’s degree in electrical engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.

• 1+ year related experience in Verilog, System Verilog or similar HVL.

• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.

• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.

• Python, Perl and C/C++ programming language experience.

• Experience using AI coding assistants like Cursor or Github copilot or Windchill

Ways to stand out from the crowd:

• Experience in driving development of large-scale ASIC floorplan is a huge plus.

• Experience building large projects from the ground up using AI tools.

• Good command of spoken English