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Google Senior Design Verification Engineer India, Karnataka, Bengaluru 689391609
18.09.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 5 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
- Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog and UVM for Application-Specific Integrated Circuits (ASIC).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience creating and using verification components and environments in a standard verification methodology such as UVM.
- Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.
- Experience with Google Line System (GLS), low-power DV, and support of SOC DV.
- Experience with performance verification of ASICs and ASIC components, ASIC standard interfaces and memory system architecture, Low Power Double Data Rate (LPDDR).
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