Samsung SoC RTL Design - Memory Team 

India, Karnataka, Bengaluru 

687761747

Key responsibilities includes (but not limited to):
• Architecture, Micro-Architecture, Design and RTL development for storage controller IP's based on UFS, NVMe, SAS, NVMeOF, eMMC and high speed peripheral bus standards such as PCIe
• Interfacing with cross functional teams like Verification, Validation and FW
• Ensuring quality of design using Lint and CDC checks
• Synthesis, Area and power optimization
• Developing the timing constraints (SDC) and ECO scripts. Follow the design process and checklists to ensure quality deliverables and reuse.
. Experience 6 to 15 Years

Role and Responsibilities

• Experience in leading the team technically

• Experience in Architecture, Micro-Architecture, Designing and RTL coding using Verilog /System Verilog/VHDL

• Working experience in complex IP Design in the High speed serial protocols like UFS, PCIe, SAS, NVMe, Fabrics

• Design QC using lint/CDC/DFT. Compile, elaboration and simulations for QC

• Experience with VCS, NCSIM, Verdi and Spyglass

• Experience in synthesis using Synopsys Design Compiler (DC) and developing timing constraints (SDC) and Timing analysis

• Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management

• Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip) and ARM CPU Architectures