Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal verification techniques.
Experience working with mixed signal (AMS/DMS) designs and mixed mode verification.
Experience in creating detailed block-level design verification strategies and plans.
Experience in one or more scripting languages (e.g., Python, etc.).
Experience creating/using verification components and environments in methodology (e.g., UVM, VMM, OVM).
Knowledge of analog design basics and experience writing SystemVerilog models of analog blocks using advanced techniques (e.g., real-number modeling (RNM), Verilog-AMS, etc.).