Nvidia Physical Design VLSI - New College Grad 

China, Shanghai 

671795657

China, Shanghai

China, Beijing

• Analysis on placement, routing, timing, clock, power, noise and DFM and provide optimization strategy

• Work on full chip clock distribution

• Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.

• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• MSEE in CS/EE/ME

• Basic knowledge of VLSI digital design backend work flow

• Basic device model, processing technology, timing, noise and power in chip design

Ways to stand out from the crowd:

• Hands-on experiences in EDA software from Synopsys(DC/ICC2/STAR-RC/PT/ICV),Cadence(Genus/Innovus/Quantus/Tempus/PVS),ANSYS (Seahawk/Redhawk) etc is a plus

• Hands-on background in DL/ML projects/programs is a plus.