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Google ASIC Design Verification Engineer Machine Learning 
United States, California, Sunnyvale 
650945205

01.04.2024
Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Madison, WI, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
Minimum qualifications:
  • Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
  • Experience with SystemVerilog (e.g. SystemVerilog Assertions or functional coverage).

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering.
  • Experience with Universal Verification Methodology (UVM).
  • Experienced with the full verification life cycle.