Cisco Senior ASIC Design Engineer 

Egypt, Al Qalyubiya, Shubra al Khayma 

650089758

• Author design specifications and participate in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements
• Help define, evolve, and support our design methodology.
• Develop and analyze functional coverage.
• Collaborate with verification team to address design bugs and close code coverage.
• Work closely with physical design team to close timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post silicon validation tests in the lab.

Minimum Qualifications:

• Bachelor’s or Master’s degree in Electrical or Computer engineering.
• Significant experience in ASIC Design (5+ years of experience)
• Excellent Verilog/System Verilog programming skills.

• Strong interactive and waveform debug skills.
• Good written and verbal communication skills.
• Collaborative and team-focused with the commitment to learn and grow.
• Scripting experience (Python, Perl, TCL, shell programming) highly desirable.